The invention relates to Programmable Logic Devices (PLDs). More particularly, the invention relates to power-up and enable control circuits for interconnection arrays in PLDDs
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. FIG. 1 is a simplified illustration of one type of PLD, the Field Programmable Gate Array (FPGA). An FPGA typically includes an array of configurable logic blocks (LBs 101a-101i) and programmable input/output blocks (I/Os 102a-102d). The LBs and I/O blocks are interconnected by a programmable interconnection array that includes a large number of interconnect lines 103 interconnected by programmable interconnect points (PIPs 104, shown as small circles in FIG. 1). PIPs are often coupled into groups (e.g., group 105) that implement multiplexer circuits selecting one of several interconnect lines to provide a signal to a destination interconnect line or logic block. Some FPGAs also include additional logic blocks with special purposes (not shown), e.g., DLLs, RAM, and so forth.
The interconnection array, LBs, I/O blocks, and other logic blocks are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the interconnection array and logic blocks are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
FIG. 2 is a simplified illustration of another type of PLD called the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more logic blocks (LBs 201a-201h) connected together and to input/output blocks (I/Os 202a-202f) by a programmable interconnection array (203). Each logic block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. The interconnection array includes many multiplexer circuits 205, each including several PIPs 204. In each multiplexer circuit 205, only one PIP 204 is enabled. The enabled PIP selects one of the many input signals provided to the interconnection array, and the selected input signal is provided as the output signal from the multiplexer circuit 205.
In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static RAM cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
PLD interconnection arrays typically include large numbers of multiplexer circuits that implement the programmable paths between the logic blocks. FIG. 3 illustrates several of these multiplexer circuits 301-303, selecting from among the signals on interconnect lines IN0-INn. (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.)
In many PLD applications, large numbers of these multiplexer circuits (and the resources driven by the multiplexer circuits) are not used even when the PLD is configured. Thus, to prevent floating nodes from occurring in a configured PLD, it is desirable for unused multiplexer circuits to provide a known value of either one (power high) or zero (ground). Further, after power-up but prior to configuration of the PLD, the multiplexer circuits preferably also provide a known value. Finally, some known multiplexer circuits also accept an enable signal, which either enables the circuit, or, alternatively, disables the circuit by forcing the multiplexer output signal to a known value. This enable signal allows the multiplexer circuits to be disabled during power-up, for example. Thus, multiplexer circuits in PLD interconnection arrays often include power-up and enable control circuits to provide some or all of these functions.
FIG. 4 is a schematic diagram of a known power-up control circuit that can be used in a PLD interconnection array. The control circuit of FIG. 4 includes a multiplexer circuit 401. The contents of memory cells SRAM_0-SRAM_m control transistors T_0-T_m to select one of the input signals IN_0-IN_m, and to place the selected signal on output terminal MUX_OUT. Coupled between output terminal MUX_OUT and power high VCC is a pull-up PU. A configuration memory cell SRAM_PU drives inverter IPU, which in turn controls pull-up PU. Coupled between output terminal MUX_OUT and ground GND is a pull-down PD. A configuration memory cell SRAM_PD drives inverter IPD, which in turn controls pull-down PD.
The control circuit of FIG. 4 functions as shown in Table 1.
In this example, in a blank (unconfigured) device, the contents of all memory cells are zero. Thus, pull-up PU is disabled, and pull-down PD is enabled, pulling output terminal MUX_OUT low. An output terminal that is low by default is generally preferred for a control circuit in a PLD interconnection array, because configuration of the PLD can occur at very low values of power high VCC. Further, to reduce die size both pull-up PU and pull-down PD are preferably minimum-sized devices. Because an N-channel transistor has a lower resistance than a similarly-sized P-channel transistor, pull-down PD is generally faster than pull-up PU. Therefore, the initialization process takes place more rapidly when the default or blank value is zero.
As previously described, typically in a blank PLD all memory cells store zero (low) values. However, as power is first applied to the PLD (i.e., during xe2x80x9cpower-upxe2x80x9d) the memory cells can xe2x80x9cwake upxe2x80x9d in either state. Therefore, when the circuit of FIG. 4 is used, during power-up some control circuits are driving high values while others are driving low values. Contention can occur, with the consequent undesirable current flow and even, potentially, resulting damage to the PLD. Therefore, an enable signal is often provided to disable the control circuit until after power-up, as in the circuit of FIG. 5.
The power-up and enable control circuit of FIG. 5 includes an enable terminal IA_ENB. When signal IA_ENB is high (e.g., during power-up), output signal MUX_OUT is forced low. When signal IA_ENB is low (e.g., after power-up is complete), the memory cells control the operation of the circuit as described in connection with the circuit of FIG. 4.
The control circuit of FIG. 5 includes a multiplexer circuit 501, which includes memory cells SRAM_O-SRAM_m, inverters I_0-I_m, NOR gates Nxe2x80x940-N_m, and transistors T_0-T_m. When enable signal IA_ENB is low, the contents of memory cells SRAM_0-SRAM_m control transistors Txe2x80x940-T_m to select one of the input signals IN_0-IN_m, and to place the selected signal on output terminal MUX_OUT. When enable signal IA_ENB is high, all of transistors T_0-T_m are disabled (off), and multiplexer circuit 501 does not drive circuit output terminal MUX_OUT.
Coupled between output terminal MUX_OUT and power high VCC is a pull-up PU. A configuration memory cell SRAM_PU drives inverter SPU, which, when enable signal IA_ENB is low, controls pull-up PU through NOR gate NOPU and inverter IPU. When enable signal IA_ENB is high, pull-up PU is off. Coupled between output terminal MUX_OUT and ground GND is a pull-down PD. A configuration memory cell SRAM_PD drives inverter SPD, which, when enable signal IA_ENB is low, controls pull-down PD through NOR gate NOPD and inverter IPD. When enable signal IA_ENB is high, pull-down PD is on.
The control circuit of FIG. 5 functions as shown in Table 2. In Table 2 (and in the other tables herein), an xe2x80x9cXxe2x80x9d entry denotes a xe2x80x9cdon""t carexe2x80x9d value, while an entry of xe2x80x9cIN_#xe2x80x9d means that the value on output terminal MUX_OUT is provided by the driver circuit (in FIG. 5, multiplexer circuit 501).
During power-up, the circuit is disabled by setting enable signal IA_ENB high. Regardless of the initial values of memory cells SRAM_PU and SRAM_PD, pull-up PU is disabled (off), while pull-down PD is enabled (on), and signal MUX_OUT goes low.
In a blank device, the circuit is enabled by setting enable signal IA_ENB low. However, the contents of all memory cells are low. Therefore, none of transistors T_0-T_m is on (i.e., multiplexer circuit 501 does not drive output terminal MUX_OUT), pull-up PU is disabled, and pull-down PD is enabled. Signal MUX_OUT is low.
After configuration, if memory cells SRAM_PU and SRAM_PD both store high values, pull-up PU is enabled, and pull-down PD is disabled. Signal MUX_OUT is high. If memory cells SRAM_PU and SRAM_PD both store low values, pull-up PU is disabled, and pull-down PD is enabled. Signal MUX_OUT is low. In both of these cases, care should be taken not to configure multiplexer circuit 501 to drive signal MUX_OUT to an opposing value, because that would cause contention on the output terminal MUX_OUT.
If memory cell SRAM_PU stores a low value and memory cell SRAM_PD stores a high value, both pull-up PU and pull-down PD are off. The value on terminal MUX_OUT is supplied by multiplexer circuit 501 and controlled by memory cells SRAM_0-SRAM_m. It is not supported to load a high value into memory cell SRAM_PU and a low value into memory cell SRAM_PD, because both pull-up PU and pull-down PD would be enabled, causing contention at output terminal MUX_OUT.
The circuit of FIG. 5 functions well when used with the 5-transistor memory cell illustrated in FIG. 6. The memory cell of FIG. 6 includes one weak inverter I_WEAK and one strong inverter I_STRONG. This memory cell has the advantage of being easy to flip by writing a new value through transistor T1, because node SRAMB_n is driven by the weak inverter I_WEAK. However, the inverted memory cell output signal (SRAMB_n) is not very powerful, and it is already heavily loaded by driving the more powerful inverter I_STRONG, which has larger transistors. Therefore, inverters I_0-I_m, SPU, and SPD in the circuit of FIG. 5 are useful in overcoming this weakness.
However, some PLDs use the 6-transistor memory cell shown in FIG. 7. The memory cell of FIG. 7 includes two weak inverters (I_WEAK1, I_WEAK2), e.g., two inverters that include minimum-sized transistors. Neither transistor is more heavily loaded within the memory cell, so either output signal can be used to drive an external circuit. Therefore, the extra inverters (I_0-I_m, SPU, and SPD) are not needed. The circuit of FIG. 5 can therefore be simplified as shown in FIG. 8.
The control circuit of FIG. 8 is similar to that of FIG. 5, except that inverters I_0-I_m, SPU, and SPD have been removed and inverted values from the configuration memory cells are used. (The name SRAMB_x as applied to a memory cell in the present application implies that the inverse output of the memory cell is used rather than the true value, as was the case for memory cell SRAM_x.) Table 3 shows the functionality of the control circuit of FIG. 8. Note that in Table 3, a value of xe2x80x9c1xe2x80x9d specified for memory cell SRAMB_PU, for example, means that the inverted output signal is high. Therefore, when a value of xe2x80x9c1xe2x80x9d is specified, the memory cell actually stores a low value, e.g., in a blank device after power-up.
FIG. 9 illustrates another known control circuit for a PLD interconnection array. The circuit of FIG. 9 is similar to the circuit of FIG. 8, but requires two fewer transistors to implement. Note that the CMOS implementation of power-up and enable portion 802 (FIG. 8) uses 14 transistors, while the CMOS implementation of corresponding portion 902 (FIG. 9) uses 12 transistors. NOR gates NOPU and NOPD and inverters IPU and IPD are replaced by NAND gates NAPU and NAPD, while the inputs to this portion of the circuit are inverted by using the true, rather than the inverse, values from memory cells SRAM_PU and SRAM_PD. The enable signal is inverted by inverter 903. The functionality of the control circuit of FIG. 9 is the same as that of the circuit shown in FIG. 5. Therefore, the functionality of the control circuit of FIG. 9 is shown in Table 2.
PLD interconnection arrays typically include large numbers of power-up and enable control circuits. Thus, area savings in these circuits can translate to significant area savings in the PLD overall, thereby reducing the cost of the device. Therefore, it is desirable to provide area-efficient power-up and enable control circuits in the interconnection arrays of PLDs.
The invention provides area-efficient power-up and enable control circuits that can be used, for example, in PLD interconnection arrays. Compared to prior art circuits that use 12 or 14 transistors in addition to the driver circuit and memory cells, the circuits of the invention use as few as four transistors to provide similar functionality.
According to a first embodiment, a control circuit includes an enable input terminal, a control circuit output terminal, a pull-up control input terminal, a pull-down control input terminal, a driver circuit, first and second pull-ups, and first and second pull-downs. The driver circuit has an output terminal coupled to the control circuit output terminal. The first and second pull-ups are coupled in series between the control circuit output terminal and a power high, the first pull-up having a gate terminal coupled to the enable input terminal and the second pull-up having a gate terminal coupled to the pull-up control input terminal. The first and second pull-downs are coupled in parallel between the control circuit output terminal and a ground, the first pull-down having a gate terminal coupled to the enable input terminal and the second pull-down having a gate terminal coupled to the pull-down control input terminal. In some embodiments, the first and second pull-ups are P-channel transistors and the first and second pull-downs are N-channel transistors.
In some embodiments, the enable input terminal provides an active-low enable signal for the control circuit such that when the enable signal is high the control circuit output terminal consistently provides a low value. In some embodiments, the enable input terminal provides an active-high enable signal for the control circuit such that when the enable signal is low the control circuit output terminal consistently provides a high value.
In some embodiments, the driver circuit is a multiplexer circuit. In some of these embodiments, the multiplexer circuit forms a portion of a programmable interconnection array in a programmable logic device (PLD), e.g., a field programmable gate array (FGPA) or a complex programmable logic device (CPLD). In some of these embodiments, the control circuit further includes first and second configuration memory cells respectively coupled to the pull-up control input terminal and the pull-down control input terminal. In some embodiments, prior to configuration of the PLD the first and second configuration memory cells provide high values to the pull-up control input terminal and the pull-down control input terminal, and the control circuit output terminal provides a low value. In other embodiments, prior to configuration of the PLD the first and second configuration memory cells provide low values to the pull-up control input terminal and the pull-down control input terminal, and the control circuit output terminal provides a high value.
According to another embodiment of the invention, a control circuit includes an enable input terminal, a control circuit output terminal, a pull-up control input terminal, a pull-down control input terminal, a driver circuit, first and second pull-ups, and first and second pull-downs. The driver circuit has an output terminal coupled to the control circuit output terminal. The first and second pull-ups are coupled in parallel between the control circuit output terminal and a power high, the first pull-up having a gate terminal coupled to the enable input terminal and the second pull-up having a gate terminal coupled to the pull-up control input terminal. The first and second pull-downs are coupled in series between the control circuit output terminal and a ground, the first pull-down having a gate terminal coupled to the enable input terminal and the second pull-down having a gate terminal coupled to the pull-down control input terminal.
According to another embodiment of the invention, a control circuit includes an enable input terminal; a control circuit output terminal; a pull-up control input terminal; a pull-down control input terminal; first and second internal nodes; a driver circuit; first, second, and third pull-ups; a first pull-down, and first and second pass-gates. The driver circuit has an output terminal coupled to the control circuit output terminal. The first pull-up is coupled between the control circuit output terminal and a power high, and has a gate terminal coupled to the first internal node. The second pull-up is coupled between the first internal node and the power high, and has a gate terminal coupled to the enable input terminal. The first pass-gate is coupled between the first internal node and the pull-up control input terminal, and has a gate terminal coupled to the enable input terminal. The first pull-down is coupled between the control circuit output terminal and a ground, and has a gate terminal coupled to the second internal node. The third pull-up is coupled between the second internal node and the power high, and has a gate terminal coupled to the enable input terminal. The second pass-gate is coupled between the second internal node and the pull-down control input terminal, and has a gate terminal coupled to the enable input terminal.
In some embodiments, the first, second, and third pull-ups are P-channel transistors and the first pull-down is an N-channel transistor.
Other embodiments of the invention include PLDs having interconnection arrays that include control circuits such as those described above. These PLDs can be FPGAs, CPLDs, or other types of PLDs including PLDs yet to be developed.